Modern chip fabrication techniques impose restrictions on the density of conductors on a chip. These restrictions are usually implemented as design rules that define square “tiles” of a certain size and minimum and maximum allowable densities for those tiles. The density of a tile is the summation of the area of all metal objects in the tile divided by the area of the tile. A chip design must meet these before it can be taped out and sent to fabrication.
The size of the tile defined by the design rules have rapidly been getting smaller at each technology node, falling at an accelerated rate; much faster than the minimum feature size of objects in the tile. The minimum density rules are checked for and met by metal filler tools in the final phase of the chip design flow. These tools examine the design on a tile-by-tile basis and add metal to those tiles that are below the minimum allowed density. To be able to function correctly, these tools need to be able to accurately calculate the density of all tiles in the design. Certain other upstream tools such as power-routers, also need to be able to estimate the density of tiles in their region of operation. This is to ensure that they do not create any tiles that have a higher density than the maximum allowed density.
FIGS. 1 and 2 are diagrams illustrating conventional examples of where tool needs to calculate the density of a tile. In this example, a tool needs to ascertain the density of a tile 10 prior to inserting a wire 12 adjacent to a block 14 of cells (not shown) in an integrated circuit design. More specifically, the area of each object in the area of the block 14 that overlaps with the tile 10 has to be calculated and summed.
In a flat physical design, the computation of density for the tile 10 is a simple operation that is typically accomplished using a layout view of the block 14, as shown in FIG. 1. In a flat physical design, the block primarily comprises many standard, but intricate, cells having many small metal objects of different shapes. The layout view contains all the information necessary for describing all the metal objects in every cell. In this example, block 14 is shown comprising three large metal areas 16 formed by metal objects in contiguous groups of cells.
The density for the tile 10 is calculated by opening the layout view and by simply summing the areas of all metal objects that lie within the outline of the tile 10 and dividing that sum by the area of the tile 10 itself.
Most designs today, however, are hierarchical in nature and accurate calculation of density becomes a problem. In hierarchical designs, groups of standard cells may be grouped into larger cells, which may also be called a block. An example of a large hierarchical block of cells is a hard macro. In hierarchical designs, accurate calculation of density becomes a problem. While in flat designs, the cell size is a small percentage of the tile size, but in hierarchical designs, the tile may be a small fraction of a large block of cells.
In hierarchical designs, hierarchical blocks are represented by a simplified routing abstraction view, as shown in FIG. 2. The routing attraction view is simplified from the layout view in that it approximates many adjacent metal objects as large blocks 18. Objects found in these routing abstractions are either simplified bloated versions of the real objects or are blockages: place-holder objects occupying regions that are not to be routed over. As a result, metal area sum calculations that use routing abstractions tend to overestimate density and are inaccurate. Also, the large number and complicated geometries of objects in the routing abstraction slow down density computation. Using the original layout view of the block 15 as in FIG. 1, results in accurate density calculations, but at too high a cost of run-time to be a feasible solution due to all the area calculations required for the many individual metal objects.
Accordingly, what is needed is a way to efficiently calculate the density of hierarchical blocks in designs with acceptable accuracy. The present invention addresses such a need.